1. Field of the Invention
The present invention relates generally to data conversion circuitry and in particular to a continuous time comparator circuit which compares a differential analog input to a reference voltage.
2. Description of Related Art
In many analog circuits, particularly where analog to digital conversion is required, an analog input voltage must be compared to a fixed reference voltage. Moreover, in high speed and high precision circuits, signals which are being processed are kept in differential form. Thus, for example, if a signal Vin is to be processed, the signal is divided into what is referred to in the present application as a positive (or first) component (Vinp) and a negative (or second) component (Vinn). Signal Vin is thus represented by the difference between the positive and negative components. In that case, to compare Vin and a reference Vref, it is necessary for the comparison circuitry to compare Vinp and Vinn with Vref. In some applications, Vref is also in differential form and includes a positive component Vrefp and a negative component Vrefn. In that event, the comparator circuitry must compare the difference between Vinp and Vinn with the difference between Vrefn and Vrefp. The same result can be achieved by comparing the difference of Vrefn and Vinn with the difference of Vrefp and Vinp. Also, the same result can be achieved by summing Vinn and Vrefp and summing Vinp and Vrefn and comparing the two sums.
Referring to the drawings, FIG. 1 is circuit diagram of a prior art comparator circuit for comparing a differential input Vin with a differential reference voltage Vref. Two differential transistor pair are used, including a first pair made up of transistors 10A and 10B and a second pair made up of transistors 12A and 12B. The two pair share a load with includes resistors R1 and R2. The voltage drop across resistor R1 is compared to the voltage drop across resistor R2 by a comparator stage 18 which provides a digital output which is high, near voltage VDD, when input voltage Vin is greater than reference Vref, and which is low, near VSS, when the input voltage is less than Vref.
The voltage drop across resistor R1 is the sum of currents I1 and I3 and the voltage drop across resistor R2 is the sum of the currents I2 and I4. Thus, the voltage drop across R1 is related to the sum of Vinp and Vrefn and the voltage drop across R2 is related to the sum of Vinn and Vrefp. As noted above, by comparing these two sums, the relative magnitudes of Vin and Vref can be ascertained. This operation is carried out by comparator stage 18 where output Vo is indicative of the relative magnitudes.
The two differential stages of the FIG. 1 comparator circuit operate to convert input voltages to currents, a conversion which is non-linear in nature. In addition, the addition of the currents are non-linear. Thus, the common mode voltage of Vref, the average of Vrefp and Vrefn, must be equal to the common mode voltage of Vin, the average of Vinp and Vinn or the FIG. 1 circuit will not operate properly. In many instances, however, the Vin is the output of a previous stage where the differential voltage of Vin is very accurate, but the common mode voltage accuracy is significantly more relaxed. In such cases, the common mode voltage of Vin can be a few hundred millivolts away from the nominal value thereby severely degrading the accuracy of the comparator circuit.
FIGS. 2A and 2B show another type of comparator circuit which only utilizes a single differential pair made up of transistors 20A and 20B. A pair of input capacitors C1 and C2, together with the inputs of the differential pair, are connected to a transistor switch array (not depicted). The comparator circuit switches between an initialize state and a compare state. Thus, the FIGS. 2A/2B circuit differs in this respect from the continuous-time comparator circuit of FIG. 1.
In the initialize state, shown in FIG. 2A, the switch array causes first terminals of capacitors C1 and C2 to be connected to Vrefp and Vrefn, respectively and the second terminals to be connected to ground. Thus, a voltage related to Vrefp and Vrefn is placed on capacitors C1 and C2, respectively. In addition, the inputs of differential pair 20A/20B are grounded.
In the compare state, shown in FIG. 2B, all of the closed transistor switches are opened. Soon thereafter, the switch array causes the first terminals of capacitors to be connected to Vinp and Vinn, respectively, and the second terminals to be connected to the respective inputs of the differential stage. The voltage applied to the gate of differential transistor 20A will thus be related to the difference between Vrefp and Vinp and the voltage applied to the gate of transistor 20B will thus be related to the difference between Vrefn and Vinn. The differential stage will amplify the difference between the two values stored on capacitors C1 and C2. The amplified difference is forwarded to a comparator stage 24 which produces a value Vo related to the relative magnitudes of Vref and Vin.
Although the FIGS. 2A/2B comparator circuit is free from the common mode voltage dependency of the FIG. 1 circuit, the FIGS. 2A/2B circuit possesses a serious drawback other than not being continuously operable. The Vinp and Vinn terminals are disturbed every time the capacitors C1 and C2 are connected to and disconnected from the terminals because the terminals must provide the current used to charge and discharge the capacitors. If Vin is being processed by other circuits, inaccurate results may be obtained since Vin has been affected by the switched capacitor circuit. The same degradation can occur on the Vref terminals as they also have to supply charge and discharge currents. Perhaps more importantly, a charge created by the switching signals for the switch array (not depicted) will tend to feed through by way of the switch capacitances thereby disturbing both Vin and Vref.
The present invention overcomes many of the shortcomings of the prior art comparator circuits previously described. A continuous-time comparator circuit is disclosed having a single differential stage and which is not subject to the common mode requirements associated with certain prior art comparator circuits noted above. These are other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
A comparator circuit and related method are disclosed for comparing a differential input signal with a reference signal. The comparator circuit includes first and second MOS transistors connected as a differential pair and having gates connected to receive first and second components, respectively, of the differential input signal. The first and second transistors have respective transistors constants, K1 and K2, that differ. Typically, the ratio of K2/K1 is at least 1.1 and preferably closer to 2-3.
A tail current source is connected to the sources of the first and second MOS transistors, with the current source output current being related to the reference signal. Preferably, the current output is related to the square of the reference signal. A comparator stage is included that is configured to provide a digital output indicative of the relative magnitude of the reference signal and differential input signal. The comparator stage preferably compares the relative magnitude of the drain-source currents of the first and second MOS transistors.